Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission

This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation

Real-Time Generation of Standard-Compliant DVB-T Signals

This paper proposes and discusses two software implementations of the DVB-T modulator, using C++ and MATLAB, respectively. All the key features of the DVB-T standard are included. The C++ DVB-T modulator, incorporated into the Iris framework developed by Trinity College of Dublin, works in real time on an Intel Core i7 2.4 GHz CPU with the Iris testbed. The MATLAB-based DVB-T modulator is coupled with a receiver implementation with channel estimation, equalization, soft-output demapping and channel decoding. The validation step demonstrates that the proposed DVB-T software implementations generate standard-compliant DVB-T signals that are correctly received by commercially available TV sets and USB dongles. The software code for the Iris-based C++ modulator, and for the MATLAB-based modulator and receiver, has been made publicly available under the GNU license

Factor graph based detection approach for high-mobility OFDM systems with large FFT modes

In this article, a novel detector design is proposed for orthogonal frequency division multiplexing (OFDM) systems over frequency selective and time varying channels. Namely, we focus on systems with large OFDM symbol lengths where design and complexity constraints have to be taken into account and many of the existing ICI reduction techniques can not be applied. We propose a factor graph (FG) based approach for maximum a posteriori (MAP) symbol detection which exploits the frequency diversity introduced by the ICI in the OFDM symbol. The proposed algorithm provides high diversity orders allowing to outperform the free-ICI performance in high-mobility scenarios with an inherent parallel structure suitable for large OFDM block sizes. The performance of the mentioned near-optimal detection strategy is analyzed over a general bit-interleaved coded modulation (BICM) system applying low-density parity-check (LDPC) codes. The inclusion of pilot symbols is also considered in order to analyze how they assist the detection process